Design of 3 bit Asynchronous/Ripple up counter

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Sequential Circuit Design 

A.Design of 3-bit Asynchronous up counter (using IC 7476) 

3-bit Asynchronous up counter using IC 7476

1. Design of Asynchronous/Ripple counter

Problem Statement:
Design 3 bit Asynchronous Up counter using IC-7476 
(Duel JK-FF-Negative edge triggered)

Design:
No. of bits=3
No. of FFs=3
No of States of counter: 8 (0 to 7)

Truth table:

FF-output Qc (MSB)	FF-output Qb	FF-output Qa (LSB)
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1