Design of 3-bit Asynchronous Down counter (using IC 7476)

Sequential Circuit Design 

A. Design of 3-bit Asynchronous Down counter (using IC 7476) 

1. Design of Asynchronous/Ripple counter
Problem Statement:
Design 3 bit Asynchronous Down counter using IC-7476 
(Duel JK-FF-Negative edge triggered)

Design:

No. of bits=3
No. of FFs=3
No of States of counter: 8 (7 to 0)







Truth table/State table:

FF-output Qc (MSB)	FF-output Qb	FF-output Qa (LSB)
1	1	1
1	1	0
1	0	1
1	0	0
0	1	1
0	1	0
0	0	1
0	0	0